1. Field of the Invention
The present invention relates to a method of manufacturing a silicon on insulator (hereinafter, referred to as SOI) which is essential for implementing a semiconductor integrated circuit having ultra large scale integration, very high speed, and low power consumption characteristics, and more particularly, to a method of manufacturing an ultra thin SOI substrate having a uniform thickness and an interface characteristic of high quality which are essential in manufacture of an nano-class semiconductor device.
2. Discussion of Related Art
In general, an SOI substrate has been developed as a substrate of a next-generation electronic device which is capable of overcoming problems such as unstable insulation between devices and occurrence of parasitic capacitance of the conventional silicon substrate when a large mount of electronic devices are integrated.
A structure of the SOI substrate means that an insulating layer is formed on a silicon wafer and a single crystalline silicon layer is present thereon. In a broad sense, the structure of the SOI substrate means that a silicon single crystal is formed on top of the SOI substrate regardless of kinds of a lower substrate and an insulating layer.
A technique of manufacturing such an SOI substrate has been progressed with a research of silicon on sapphire (SOS) in 1960s, and zone-melting and recrystallization (ZMR) method, a porous silicon oxidation method, a lateral epitaxial growth method of silicon, and so forth have been researched in its initial development. However, a separation by implantation of oxygen (SIMOX) technique, a unibond technique using smart cut, an epitaxial layer transfer technique or the like have been a main stream in recent years.
According to the SIMOX technique of the related art, oxygen of about 1×1017 to 9×1017 atoms/cm2 is injected into the silicon, which is then subjected to annealing and oxidation at a high temperature of about 1300° C. to 1500° C. for recrystallization of the silicon and stability of the buried oxidation layer and defect removal.
However, according to the SIMOX technique of the related art, it is difficult to form a silicon layer having a uniform thickness and a low concentration of impurity, and a high defect density at an interface and a region near the interface, and poor surface roughness can adversely affect an device.
In addition, according to the UNIBOND technique of the related art, a smart cut method is employed by which hydrogen ions are first injected into a silicon wafer in which an insulating layer is already formed, which is then bonded with another silicon wafer to make a lower part of the hydrogen ion injection location of the silicon wafer fall off through a subsequent annealing process to thereby form a thin silicon layer, so that effects such as higher crystal quality, higher BOX quality, less surface roughness and low price process in thick film SOI can be expected as compared to other methods of the related art, however, thickness uniformity is still required, and productivity is degraded due to several processes such as a chemical mechanical polishing (CMP) process.
In addition, according to the ELTRAN technique of the related art, a porous silicon layer is first formed on a silicon wafer, and a single crystalline silicon-epitaxial-layer is formed on the resultant structure using an epitaxial process. Thereafter, the resultant structure is bonded with the silicon wafer where an insulating layer is formed, and the whole silicon wafer of the wafer where a single crystal is formed and the porous silicon layer are removed by polishing and etching processes to thereby obtain a planarized silicon layer. The technique is relatively advantageous in control of a thickness of the silicon layer, however, it is not good for matching with a complementary metal oxide semiconductor (CMOS) process of the related art, and is limited to some applications due to degradation of film quality, particle occurrence, poor surface roughness, degraded reliability, or the like.
As described above, the conventional techniques (SIMOX, UNIBOND, and ELTRAN or the like) for manufacturing an ultra thin body (UTB) SOI substrate used in manufacture of the UTB SOI CMOS device, do not completely meet requirements of the UTB SOI wafer which requires control on a uniform thickness, a low defect density, and an upper silicon thickness of several nanometers in nano-class devices.